Computer aided design (CAD) software is used by digital electronic system designers to predict the behavior of digital electronic systems before fabricating integrated circuits containing the digital electronic systems. Very large-scale integration (VLSI) allows large numbers of circuits to be packaged in small spaces. Due to the complexity involved with VLSI circuits, VLSI circuits must be simulated before fabricating the VLSI circuits on an integrated circuit chip. Successful implementation of VLSI circuits is impossible without computer simulation of the circuits.
A typical purpose of CAD is to estimate timing and delays associated with signals operating within integrated circuits. The speed at which signals within an integrated circuits can propagate can be limited by capacitance associated with the interconnection lines within the integrated circuit. Therefore, estimations of delays associated with the interconnections within the integrated circuit is critical.
FIG. 1 shows several interconnections lines within an integrated circuit. The interconnection lines are typically arranged in a planar configuration. For example, FIG. 1 includes a first plane P1, a second plane P2 and a third plane P3. The first plane P1 includes interconnection lines 10, 11, 12. The second plane P2 includes interconnection lines 13, 14, 15. The third plane P3 includes interconnection lines 16, 17, 18.
Typically, CAD programs use 2 dimensional (2D) estimations for distributed interconnection capacitance. FIG. 2 shows the capacitive effects accounted for in a 2D estimation of the distributed interconnection capacitance associated with an interconnection line 14. The 2D distributed interconnection capacitance includes capacitors C21, C22, C23, C24, C25, C26, C27 and C28. The capacitance is only estimated in the two dimensions shown.
FIG. 3 shows a top view of the same interconnection lines shown in FIG. 2. FIG. 3 shows the 3 dimensional (3D) fringing capacitances not accounted for in typical 2D capacitive estimations. The 3D fringing capacitance includes capacitors C29, C30, C31 and C32. Most conventional CAD programs ignore 3D fringing capacitance. However, 3D fringing capacitance can have a significant effect on multi-level interconnect capacitances for interconnection lines as shown in FIG. 1. Neglecting 3D fringing capacitances can cause 20-40% errors in estimations of interconnection line capacitance.
Full 3D numerical estimations of 3D capacitance of global interconnection lines have been implemented by CAD programs. However, these 3D estimations are very complex and require extremely large amounts of computer processing time. Capacitance estimations can take over ten hours for each interconnection line. VLSI integrated circuits require a large number of interconnection lines. Therefore, full 3D estimations of global interconnection line capacitance have not been practical in the design of VLSI integrated circuits.
It is desirable to have a method of estimating distributed capacitance of interconnections within integrated circuits which is more accurate than the 2D estimations presently used in CAD programs. Furthermore, the method of estimating distributed capacitance must not require excessive amounts of computer processing time.